1. Field of the Invention
The present invention relates to a video signal synchronization signal generating apparatus, and more particularly, to a video signal synchronization signal generating apparatus as a control apparatus for a synchronization signal which serves as a display output control signal, to be used with a video reproducing device which displays a video signal of an input vertical synchronization signal having a frequency different from the frequency of a display vertical synchronization signal, and to a video signal synchronization signal generation method.
2. Description of Related Art
In general, for video reproducing devices such as flat panel displays (hereinafter abbreviated as “FPDs”), standards for period range of frequency of a vertical synchronization signal for video output (hereinafter referred to as “display vertical synchronization frequency”) are defined according to device size and/or model. And most of such standards set an extremely narrow acceptable range for the period of the vertical synchronization signal.
Meanwhile, types of video signal for reproduction on video reproducing devices such as FPDs are becoming more and more diverse, and the input vertical synchronization frequency of such a video signal is often different from display vertical synchronization frequency. For example, this is a case when video reproduction output having an input vertical synchronization frequency of 24 Hz is displayed on a FPD having a display vertical synchronization frequency of 60 Hz.
One conventionally known method for displaying such video reproduction output having an input vertical synchronization frequency of 24 Hz on a video device having a display vertical synchronization frequency of 60 Hz is to generate an input signal with 60 frames/second from a video signal made up of 24 frames/second through telecine conversion of individual frames of the video reproduction output by using 2-3 pull-down method (see Japanese Patent Application Laid-Open Publication No. 2004-1274576, for instance).
However, even when a frequency difference between the input vertical synchronization frequency and the display vertical synchronization frequency is made apparently equal by adding frames as shown in Japanese Patent Application Laid-Open Publication No. 2004-1274576, the input vertical synchronization frequency and the display vertical synchronization frequency become slightly misaligned in practice due to clock synchronization error or the like to cause an asynchronous condition. An asynchronous condition leads to a problem of significant degradation of video quality due to skipping and/or repeating of images.